Parent Log: http://ci.aztec-labs.com/4377c19df791fe00 Command: b65330ebb7ef0b78:CPUS=4:MEM=8g barretenberg/cpp/scripts/run_test.sh dsl_tests AcirHonkRecursionConstraint/1.TestFullRecursiveComposition Commit: https://github.com/AztecProtocol/aztec-packages/commit/420e0a54fb4bfe8b04d7dd479f59ed0fe3ad3b74 Env: REF_NAME=gh-readonly-queue/next/pr-14922-106f897363bb5aee27ddd091b5be9641b011c5bb CURRENT_VERSION=0.87.6 CI_FULL=1 Date: Thu Jun 12 16:08:37 UTC 2025 System: ARCH=amd64 CPUS=128 MEM=493Gi HOSTNAME=pr-14922_amd64_x3-full Resources: CPU_LIST=0-127 CPUS=4 MEM=8g TIMEOUT=600s History: http://ci.aztec-labs.com/list/history_bafe85c33b4ce4ee_next 16:08:37 Running main() from /home/aztec-dev/aztec-packages/barretenberg/cpp/build/_deps/gtest-src/googletest/src/gtest_main.cc 16:08:37 Note: Google Test filter = AcirHonkRecursionConstraint/1.TestFullRecursiveComposition 16:08:37 [==========] Running 1 test from 1 test suite. 16:08:37 [----------] Global test environment set-up. 16:08:37 [----------] 1 test from AcirHonkRecursionConstraint/1, where TypeParam = bb::UltraRollupRecursiveFlavor_<bb::UltraCircuitBuilder_<bb::UltraExecutionTraceBlocks> > 16:08:37 [ RUN ] AcirHonkRecursionConstraint/1.TestFullRecursiveComposition 16:08:37 Proving with UltraRollupHonk but no IPA claims exist. (mem: 12.00 MiB) 16:08:37 created first inner circuit (mem: 56.08 MiB) 16:08:37 Proving with UltraRollupHonk but no IPA claims exist. (mem: 56.08 MiB) 16:08:37 created second inner circuit (mem: 56.08 MiB) 16:08:37 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 56.08 MiB) 16:08:39 created first outer circuit (mem: 575.43 MiB) 16:08:39 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 575.43 MiB) 16:08:41 created second outer circuit (mem: 1054.43 MiB) 16:08:49 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2551.58 MiB) 16:09:15 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2738.18 MiB) 16:09:40 created third outer circuit (mem: 2971.82 MiB) 16:09:40 number of gates in layer 3 circuit = 1469951 (mem: 2971.82 MiB) 16:09:43 prover gates = 2097152 (mem: 4278.70 MiB) 16:09:44 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 5444.76 MiB) 16:10:33 [ OK ] AcirHonkRecursionConstraint/1.TestFullRecursiveComposition (116163 ms) 16:10:33 [----------] 1 test from AcirHonkRecursionConstraint/1 (116163 ms total) 16:10:33 16:10:33 [----------] Global test environment tear-down 16:10:33 [==========] 1 test from 1 test suite ran. (116163 ms total) 16:10:33 [ PASSED ] 1 test.