Parent Log: http://ci.aztec-labs.com/286acb54102582f4 Command: 049e4025f7cee894:CPUS=4:MEM=8g barretenberg/cpp/scripts/run_test.sh dsl_tests AcirHonkRecursionConstraint/1.TestFullRecursiveComposition Commit: https://github.com/AztecProtocol/aztec-packages/commit/27dbf3ae6582b46a4067f31ea648dfedd0d36169 Env: REF_NAME=gh-readonly-queue/next/pr-14877-a45107e7f95b675cb2768b6bcb06483b511141f4 CURRENT_VERSION=0.87.6 CI_FULL=1 Date: Thu Jun 12 20:39:37 UTC 2025 System: ARCH=amd64 CPUS=128 MEM=493Gi HOSTNAME=pr-14877_amd64_x3-full Resources: CPU_LIST=0-127 CPUS=4 MEM=8g TIMEOUT=600s History: http://ci.aztec-labs.com/list/history_bafe85c33b4ce4ee_next 20:39:37 Running main() from /home/aztec-dev/aztec-packages/barretenberg/cpp/build/_deps/gtest-src/googletest/src/gtest_main.cc 20:39:37 Note: Google Test filter = AcirHonkRecursionConstraint/1.TestFullRecursiveComposition 20:39:37 [==========] Running 1 test from 1 test suite. 20:39:37 [----------] Global test environment set-up. 20:39:37 [----------] 1 test from AcirHonkRecursionConstraint/1, where TypeParam = bb::UltraRollupRecursiveFlavor_<bb::UltraCircuitBuilder_<bb::UltraExecutionTraceBlocks> > 20:39:37 [ RUN ] AcirHonkRecursionConstraint/1.TestFullRecursiveComposition 20:39:37 Proving with UltraRollupHonk but no IPA claims exist. (mem: 12.00 MiB) 20:39:37 created first inner circuit (mem: 56.64 MiB) 20:39:37 Proving with UltraRollupHonk but no IPA claims exist. (mem: 56.64 MiB) 20:39:37 created second inner circuit (mem: 56.64 MiB) 20:39:37 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 56.64 MiB) 20:39:40 created first outer circuit (mem: 560.94 MiB) 20:39:40 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 560.94 MiB) 20:39:42 created second outer circuit (mem: 1046.94 MiB) 20:39:51 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2554.04 MiB) 20:40:16 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2733.30 MiB) 20:40:45 created third outer circuit (mem: 2971.70 MiB) 20:40:45 number of gates in layer 3 circuit = 1469951 (mem: 2971.70 MiB) 20:40:49 prover gates = 2097152 (mem: 4283.62 MiB) 20:40:50 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 5447.55 MiB)