Parent Log: http://ci.aztec-labs.com/9ccf1b6eb40a93f5 Command: 6b749196b5c0246c:CPUS=4:MEM=8g barretenberg/cpp/scripts/run_test.sh dsl_tests AcirHonkRecursionConstraint/0.TestFullRecursiveComposition Commit: https://github.com/AztecProtocol/aztec-packages/commit/77a00686be4080a71b03d68671da6c8b270b62aa Env: REF_NAME=gh-readonly-queue/next/pr-14961-fa23733be8278348dff0959c8094bcfd89eb44d5 CURRENT_VERSION=0.87.6 CI_FULL=1 Date: Thu Jun 12 10:44:51 UTC 2025 System: ARCH=amd64 CPUS=128 MEM=493Gi HOSTNAME=pr-14961_amd64_x2-full Resources: CPU_LIST=0-127 CPUS=4 MEM=8g TIMEOUT=600s History: http://ci.aztec-labs.com/list/history_0e4b4c9c338e4ee0_next 10:44:52 Running main() from /home/aztec-dev/aztec-packages/barretenberg/cpp/build/_deps/gtest-src/googletest/src/gtest_main.cc 10:44:52 Note: Google Test filter = AcirHonkRecursionConstraint/0.TestFullRecursiveComposition 10:44:52 [==========] Running 1 test from 1 test suite. 10:44:52 [----------] Global test environment set-up. 10:44:52 [----------] 1 test from AcirHonkRecursionConstraint/0, where TypeParam = bb::UltraRecursiveFlavor_<bb::UltraCircuitBuilder_<bb::UltraExecutionTraceBlocks> > 10:44:52 [ RUN ] AcirHonkRecursionConstraint/0.TestFullRecursiveComposition 10:44:52 created first inner circuit (mem: 14.00 MiB) 10:44:52 created second inner circuit (mem: 15.00 MiB) 10:44:52 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 30.00 MiB) 10:44:54 created first outer circuit (mem: 551.22 MiB) 10:44:54 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 551.22 MiB) 10:44:56 created second outer circuit (mem: 1049.22 MiB) 10:45:05 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2554.62 MiB) 10:45:30 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2740.42 MiB) 10:45:53 created third outer circuit (mem: 2954.23 MiB) 10:45:53 number of gates in layer 3 circuit = 1411875 (mem: 2954.23 MiB) 10:45:56 prover gates = 2097152 (mem: 4230.48 MiB) 10:45:57 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 5398.91 MiB) 10:46:46 [ OK ] AcirHonkRecursionConstraint/0.TestFullRecursiveComposition (114245 ms) 10:46:46 [----------] 1 test from AcirHonkRecursionConstraint/0 (114245 ms total) 10:46:46 10:46:46 [----------] Global test environment tear-down 10:46:46 [==========] 1 test from 1 test suite ran. (114245 ms total) 10:46:46 [ PASSED ] 1 test.