Parent Log: http://ci.aztec-labs.com/3b97e2842c9014dd Command: 060f2775b5406036:CPUS=4:MEM=8g barretenberg/cpp/scripts/run_test.sh dsl_tests AcirHonkRecursionConstraint/0.TestFullRecursiveComposition Commit: https://github.com/AztecProtocol/aztec-packages/commit/ddabb45f79cc171e41a0a5330544775de9fdf7fd Env: REF_NAME=gh-readonly-queue/next/pr-14983-4e03f15ca8099f25d50eddd19c4914764b84fe7b CURRENT_VERSION=0.87.6 CI_FULL=1 Date: Fri Jun 13 14:34:06 UTC 2025 System: ARCH=amd64 CPUS=128 MEM=493Gi HOSTNAME=pr-14983_amd64_x3-full Resources: CPU_LIST=0-127 CPUS=4 MEM=8g TIMEOUT=600s History: http://ci.aztec-labs.com/list/history_0e4b4c9c338e4ee0_next 14:34:06 Running main() from /home/aztec-dev/aztec-packages/barretenberg/cpp/build/_deps/gtest-src/googletest/src/gtest_main.cc 14:34:06 Note: Google Test filter = AcirHonkRecursionConstraint/0.TestFullRecursiveComposition 14:34:06 [==========] Running 1 test from 1 test suite. 14:34:06 [----------] Global test environment set-up. 14:34:06 [----------] 1 test from AcirHonkRecursionConstraint/0, where TypeParam = bb::UltraRecursiveFlavor_<bb::UltraCircuitBuilder_<bb::UltraExecutionTraceBlocks> > 14:34:06 [ RUN ] AcirHonkRecursionConstraint/0.TestFullRecursiveComposition 14:34:06 created first inner circuit (mem: 14.00 MiB) 14:34:06 created second inner circuit (mem: 15.00 MiB) 14:34:06 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 28.00 MiB) 14:34:08 created first outer circuit (mem: 555.25 MiB) 14:34:08 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 555.25 MiB) 14:34:11 created second outer circuit (mem: 1043.25 MiB) 14:34:19 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2547.45 MiB) 14:34:43 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 2741.42 MiB) 14:35:05 created third outer circuit (mem: 2962.28 MiB) 14:35:05 number of gates in layer 3 circuit = 1411875 (mem: 2962.28 MiB) 14:35:08 prover gates = 2097152 (mem: 4236.75 MiB) 14:35:09 WARNING: We are temporarily regressing prover speed by computing the verification key in the prover. This will be fixed in a followup PR. (mem: 5404.86 MiB) 14:36:00 [ OK ] AcirHonkRecursionConstraint/0.TestFullRecursiveComposition (114097 ms) 14:36:00 [----------] 1 test from AcirHonkRecursionConstraint/0 (114097 ms total) 14:36:00 14:36:00 [----------] Global test environment tear-down 14:36:00 [==========] 1 test from 1 test suite ran. (114097 ms total) 14:36:00 [ PASSED ] 1 test.